The invention relates to semiconductors and, more particularly, to silicon-on-insulator (SOI) transistor devices.
Transistors typically consist of three basic elements: the source, the gate and the drain. Current flows from the source to the drain when the gate is charged. Bipolar and MOS (metal-oxide semiconductor) are two basic types of transistors. CMOS (complementary metal-oxide semiconductor) is an extension of MOS formed by joining two transistors and different dopants in the various regions. Because of the complementary behavior in CMOS, there is no current flow through the device except when it switches. CMOS circuits therefore consume less power when compared to Bipolar counterparts which leak current in their off state. MOS has become the mainstay of chip design.
Traditionally, transistors were fabricated on bulk silicon. More recently, they are being fabricated using silicon-on-insulator (SOI) technology. The difference between conventional MOS and Silicon-on-Insulator (SOI) construction is a layer of insulating material separating the transistor's silicon junction area and the bulk silicon.
Double-gate transistors will help improve processor speed and power use by allowing better control of electrical flow across the transistor. Simply stated, transistors react to electricity and go to either an on or off state, providing the binary status necessary for computer operations. But as chips continue to shrink, single-gate transistors will experience increased electron leakage (which can keep transistors trapped in the on state), higher energy needs, and worsened electrical flow.
U.S. Patent Application No. 2002/0192911 discloses Damascene double gated transistors and related manufacturing methods. This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a self-aligned, hyper-abrupt retrograde body and a zero-parasitic, end-wall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.